1 data sheet acquired from harris semiconductor schs200b features fully static operation buffered inputs common reset positive edge clocking typical f max = 50mhz at v cc =5v,c l = 15pf, t a =25 o c fanout (over temperature range) - standard outputs . . . . . . . . . . . . . . . 10 lsttl loads - bus driver outputs . . . . . . . . . . . . . 15 lsttl loads wide operating temperature range . . . -55 o c to 125 o c balanced propagation delay and transition times signi?ant power reduction compared to lsttl logic ics hc types - 2v to 6v operation - high noise immunity: n il = 30%, n ih = 30% of v cc at v cc = 5v description the ?c4017 is a high speed silicon gate cmos 5-stage johnson counter with 10 decoded outputs. each of the decoded outputs is normally low and sequentially goes high on the low to high transition clock period of the 10 clock period cycle. the carry (tc) output transitions low to high after output 10 goes low, and can be used in conjunction with the clock enable ( ce) to cascade several stages. the clock enable input disables counting when in the high state. a reset (mr) input is also provided which when taken high sets all the decoded outputs, except ?? low. the device can drive up to 10 low power schottky equivalent loads. pinout cd54hc4017 (cerdip) cd74hc4017 (pdip, sop) top view ordering information part number temp. range ( o c) package cd54hc4017f3a -55 to 125 16 ld cerdip cd74hc4017e -55 to 125 16 ld pdip cd74hc4017nsr -55 to 125 16 ld sop notes: 1. when ordering, use the entire part number. add the suf? 96 to obtain the variant in the tape and reel. 2. wafer or die for this part number is available which meets all elec- trical specifications. please contact your local ti sales office or customer service for ordering information. 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 5 1 0 2 6 7 gnd 3 v cc cp ce tc 9 4 8 mr november 1997 - revised march 2002 caution: these devices are sensitive to electrostatic discharge. users should follow proper ic handling procedures. copyright 2002, texas instruments incorporated cd54/74hc4017 high speed cmos logic decade counter/divider with 10 decoded outputs [ /title (cd74 hc401 7) / sub- j ect (high speed cmos logic decade counte
2 functional diagram truth table cp ce mr output state ? l x l no change x h l no change x x h ??= h, ????= l l l increments counter x l no change x l no change h l increments counter note: h = high level l = low level = high to low transition = low to high transition x = don? care. ? if n < 5 tc = h, otherwise = l 3 2 4 7 1 6 5 10 0 1 2 3 4 5 6 7 14 13 15 clock clock master 9 12 11 8 9 terminal count reset enable decoded decimal out cd54/74hc4017
3 absolute maximum ratings thermal information dc supply voltage, v cc . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 7v dc input diode current, i ik for v i < -0.5v or v i > v cc + 0.5v . . . . . . . . . . . . . . . . . . . . . . 20ma dc output diode current, i ok for v o < -0.5v or v o > v cc + 0.5v . . . . . . . . . . . . . . . . . . . . 20ma dc output source or sink current per output pin, i o for v o > -0.5v or v o < v cc + 0.5v . . . . . . . . . . . . . . . . . . . . 25ma dc v cc or ground current, i cc or i gnd . . . . . . . . . . . . . . . . . . 50ma operating conditions temperature range, t a . . . . . . . . . . . . . . . . . . . . . . -55 o c to 125 o c supply voltage range, v cc hc types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2v to 6v hct types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5v to 5.5v dc input or output voltage, v i , v o . . . . . . . . . . . . . . . . . 0v to v cc input rise and fall time 2v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (max) 4.5v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (max) 6v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (max) package thermal impedance, ja (see note 3): pdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 o c/w sop package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 o c/w maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . 150 o c maximum storage temperature range . . . . . . . . . .-65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300 o c (soic - lead tips only) caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not im plied. note: 3. the package thermal impedance is calculated in accordance with jesd 51-7. dc electrical speci?ations parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units v i (v) i o (ma) min typ max min max min max high level input voltage v ih - - 2 1.5 - - 1.5 - 1.5 - v 4.5 3.15 - - 3.15 - 3.15 - v 6 4.2 - - 4.2 - 4.2 - v low level input voltage v il - - 2 - - 0.5 - 0.5 - 0.5 v 4.5 - - 1.35 - 1.35 - 1.35 v 6 - - 1.8 - 1.8 - 1.8 v high level output voltage cmos loads v oh v ih or v il -0.02 2 1.9 - - 1.9 - 1.9 - v -0.02 4.5 4.4 - - 4.4 - 4.4 - v -0.02 6 5.9 - - 5.9 - 5.9 - v high level output voltage ttl loads - - --- - - - - v -4 4.5 3.98 - - 3.84 - 3.7 - v -5.2 6 5.48 - - 5.34 - 5.2 - v low level output voltage cmos loads v ol v ih or v il 0.02 2 - - 0.1 - 0.1 - 0.1 v 0.02 4.5 - - 0.1 - 0.1 - 0.1 v 0.02 6 - - 0.1 - 0.1 - 0.1 v low level output voltage ttl loads - - --- - - - - v 4 4.5 - - 0.26 - 0.33 - 0.4 v 5.2 6 - - 0.26 - 0.33 - 0.4 v input leakage current i i v cc or gnd -6-- 0.1 - 1- 1 a quiescent device current i cc v cc or gnd 0 6 - - 8 - 80 - 160 a note: for dual-supply systems theoretical worst case (v i = 2.4v, v cc = 5.5v) speci?ation is 1.8ma. cd54/74hc4017
4 prerequisite for switching speci?ations parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units min typ max min max min max maximum clock frequency f max - 26- -5-4-mhz 4.5 30 - - 35 - 20 - mhz 6 35 - - 49 - 23 - mhz cp pulse width t w - 2 80 - - 100 - 120 - ns 4.5 16 - - 20 - 24 - ns 614- -17-20-ns mr pulse width t w - 2 80 - - 100 - 120 - ns 4.5 16 - - 20 - 24 - ns 614- -17-20-ns set-up time, ce to cp t su - 2 75 - - 95 - 110 - ns 4.5 15 - - 19 - 22 - ns 613- -16-19-ns hold time, ce to cp t h - 20- -0-0-ns 4.50- -0-0-ns 60- -0-0-ns mr removal time t rem - 25- -5-5-ns 4.55- -5-5-ns 65- -5-5-ns switching speci?ations input t r , t f = 6ns parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units min typ max min max min max propagation delay t plh, t phl c l = 50pf 2 - - 230 - 290 - 345 ns cp to any dec. out c l = 50pf 4.5 - - 46 - 58 - 69 ns c l = 15pf 5 - 19 - - - - - ns c l = 50pf 6 - - 39 - 49 - 59 ns cp to tc t plh, t phl c l = 50pf 2 - - 230 - 290 - 345 ns c l = 50pf 4.5 - - 46 - 58 - 69 ns c l = 15pf 5 - 19 - - - - - ns c l = 50pf 6 - - 39 - 49 - 59 ns ce to any dec. out t plh, t phl c l = 50pf 2 - - 250 - 315 - 375 ns c l = 50pf 4.5 - - 50 - 63 - 75 ns c l = 15pf 5 - 21 - - - - - ns c l = 50pf 6 - - 43 - 54 - 64 ns ce to tc t plh, t phl c l = 50pf 2 - - 250 - 315 - 375 ns c l = 50pf 4.5 - - 50 - 63 - 75 ns c l = 15pf 5 - 21 - - - - - ns c l = 50pf 6 - - 43 - 54 - 64 ns cd54/74hc4017
5 mr to any dec. out t plh, t phl c l = 50pf 2 - - 230 - 290 - 345 ns c l = 50pf 4.5 - - 46 - 58 - 69 ns c l = 15pf 5 - 19 - - - - - ns c l = 50pf 6 - - 39 - 49 - 59 ns mr to tc t plh, t phl c l = 50pf 2 - - 230 - 290 - 345 ns c l = 50pf 4.5 - - 46 - 58 - 69 ns c l = 15pf 5 - 19 - - - - - ns c l = 50pf 6 - - 39 - 49 - 59 ns transition time tc, dec. out t tlh ,t thl c l = 50pf 2 - - 75 - 95 - 110 ns c l = 50pf 4.5 - - 15 - 19 - 22 ns c l = 50pf 6 - - 13 - 16 - 19 ns input capacitance c in c l = 50pf - - - 10 - 10 - 10 pf maximum cp frequency f max c l = 15pf 5 - 60 - - - - - mhz power dissipation capacitance (notes 4, 5) c pd c l = 15pf 5 - 39 - - - - - pf notes: 4. c pd is used to determine the dynamic power consumption, per package. 5. p d = v cc 2 f i c l v cc 2 fo where f i = input frequency, f o = output frequency, c l = output load capacitance, v cc = supply voltage. switching speci?ations input t r , t f = 6ns (continued) parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units min typ max min max min max test circuits and waveforms note: outputs should be switching from 10% v cc to 90% v cc in accordance with device truth table. for f max , input duty cycle = 50%. figure 1. hc clock pulse rise and fall times and pulse width figure 2. hc transition times and propagation delay times, combination logic clock 90% 50% 10% gnd v cc t r c l t f c l 50% 50% t wl t wh 10% t wl + t wh = fc l i t phl t plh t thl t tlh 90% 50% 10% 50% 10% inverting output input gnd v cc t r = 6ns t f = 6ns 90% cd54/74hc4017
6 figure 3. hc setup times, hold times, removal time, and propagation delay times for edge triggered sequential logic circuits timing diagrams figure 4. figure 5. test circuits and waveforms (continued) t r c l t f c l gnd v cc gnd v cc 50% 90% 10% gnd clock input data input output set, reset or preset v cc 50% 50% 90% 10% 50% 90% t rem t plh t su(h) t tlh t thl t h(l) t phl ic c l 50pf t su(l) t h(h) c l c l p n p n pn p n d c l q c ff detail c l c l c l c l c l c l q r clock master reset clock enable ? ? ? ? ? ? ? ? ? ? terminal count 0 1 2 3 4 5 6 7 8 9 0 1 2 cd54/74hc4017
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